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Tuesday, 3 March 2015

SCHEDULE & VENUE FOR EVALUATION TEST

B9   (Lecture Hall - 806) - Timings 12:30PM - 1.00PM
B10 (Lecture Hall - 808) - Timings 12:30PM - 1.00PM
B11 (Lecture Hall - 806) - Timings 1.00 PM - 1.30 PM
B12 (Lecture Hall - 810) - Timings 1.00 PM - 1:30 PM

NOTE - All the students are instructed to reach for Test prior 10 minutes and settle down on their seats Roll Number wise.

 
SYLLABUS FOR BE MST -1

Diodes: PN Junction diode, VI characteristics, concept of barrier potential, working of diode in forward & reverse bias, knee voltage, PIV, types of breakdown (zener & avalanche breakdown), diode as an ideal switch, DC load line analysis, operating point or Q point, junction capacitance (transition & diffusion capacitance), diode clipper, diode clampers, zener diode (VI characteristics, applications), rectifier circuits (half wave, center tapped, bridge rectifiers), voltage regulation.
 
Transistors: Construction, working of NPN & PNP Transistors, Transistor operating modes, transistor configurations, VI characteristics of transistors in different configurations, transistor as an amplifier, need of biasing, transistor biasing circuits (base resistor biasing, emitter resistor biasing, potential divider biasing), multistage amplifier circuits, feedback amplifier circuits.   

Monday, 16 February 2015

LIST OF BE LAB EXPERIMENTS PERFORMED TILL DATE
1.(a) Testing of Resistors
   (b) Testing of Capacitors
   (c) Testing of Inductors

2.(a) Testing of Switches
   (b) Testing of Fuses

3. Verification of truth tables of various logic gates

4. Familarization with the basic tools in the Lab

5. To get familiar with the working knowledge of various instruments.

6. Familarization with Signal Generator & Function Generator